PIC18C801T-I/L【PDF 20/319 页】IC MCU ROMLESS A/D PWM 84PLCC

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PIC18C601/801

DS39541A-page 116

Advance Information

2001 Microchip Technology Inc.

9.6

PORTF, LATF, and TRISF

Registers

PORTF is an 8-bit wide, bi-directional port. The corre-

sponding data direction register is TRISF. Setting a

TRISF bit (= 1) will make the corresponding PORTF pin

an input (i.e., put the corresponding output driver in a

Hi-Impedance mode). Clearing a TRISF bit (= 0) will

make the corresponding PORTF pin an output (i.e., put

the contents of the output latch on the selected pin).

Read-modify-write operations on the LATF register

reads and writes the latched output value for PORTF.

PORTF pins, RF2:RF0, are multiplexed with analog

inputs. The operation of these pins are selected by

ADCON0 and ADCON1 registers.

PORTF pins, RF3 and RF5, are multiplexed with two of

the integrated chip select signals CSIO and CS1. For

PIC18C801, pin RF4 is multiplexed with chip select sig-

nal CS2, while for PIC18C601, it is multiplexed with

system bus signal A16. For PIC18C801 devices, both

CSEL2 and CSELIO registers must set to all zero, to

enable these pins as I/O pins, while for PIC18C601

devices, only CSELIO register needs to be set to zero.

For PIC18C601 devices, pin RF4 can only be config-

ured as I/O when the EBDIS bit is set and execution is

taking place in internal Boot RAM.

PORTF pins, RF7:RF6, are multiplexed with the sys-

tem bus control signal UB and LB, respectively, when a

device with 16-bit bus execution is used. These pins

can be configured as I/O pins by setting WM bits in the

MEMCON register to any value other than ’01’.

EXAMPLE 9-6:

INITIALIZING PORTF

EXAMPLE 9-7:

PROGRAMMING CHIP

SELECT SIGNALS

FIGURE 9-11:

RF2:RF0 PINS BLOCK

DIAGRAM

Note 1: On

Power-on

Reset,

PORTF

pins

RF2:RF0 default to A/D inputs.

2: On

Power-on

Reset,

PORTF

pins

RF7:RF3

for

PIC18C801

and

pins

RF7:RF5, RF3 for PIC18C601, default to

system bus signals.

CLRF

PORTF

; Initialize PORTF by

; clearing output

; data latches

CLRF

LATF

; Alternate method

; to clear output

; data latches

MOVLW

0Fh

;

MOVWF

ADCON1

; Set PORTF as digital I/O

MOVLW

0CFh

; Value used to

; initialize data

; direction

MOVWF

TRISF

; Set RF3:RF0 as inputs

; RF5:RF4 as outputs

; RF7:RF6 as inputs

; Program chip select to activate CS1

; for all address less than 03FFFFh,

; while activate CS2 for rests of the

; addresses

; CSEL2 register is secured register.

; Before it can be modified it,

; combination lock must be opened

MOVLW 20h

; Preload WREG with

; correct CSEL2 valu

BCF INTCON, GIE

; Disable interrupts

CALL UNLOCK

; Now unlock it

; Lock is open.

Modify CSEL2...

MOVWF CSEL2

; Lock is closed

BSF INTCON, GIE

; Re-enable interrupts

; Chip select is programmed.

UNLOCK

BSF PSPCON, CMLK1

BSF PSPCON, CMLK0

RETURN

Data Bus

WR LATF

WR TRISF

Data Latch

TRIS Latch

RD TRISF

RD PORTF

VSS

VDD

I/O pin

Analog

Input

Mode

Input

Buffer

To A/D Converter

RD LATF

WR PORTF

Note:

I/O pins have diode protection to VDD and VSS.

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